Conventional circuit capture and simulation schemes are limited in their abilities to scale designs and are typically restricted by their fixed port maps, with a specific number of ports having specific names and types. Such approaches require that all input ports be connected in some functionally correct manner and do not provide the option of dynamic ports wherein the ports and their characteristics can adapt to system requirements. Moreover, conventional schematic capture schemes provide libraries of components with fixed parameters. As a result, designs of products, such as field programmable gate arrays and other custom circuits are constrained to a narrow range of implementations and cannot be optimized based on the dataflow in the system. In addition, such design systems typically comprise low-level components whose interaction with peer components must be manually negotiated by the user.
A system according to the invention seeks to avoid such limitations by providing a designer the ability to create designs based on dataflow, as represented in components responsive to well defined intercommunication protocols. A system according to the invention conceptually behaves in a manner analogous to that of a Petri Net. According to the invention, protocols are derivative of several canonical forms. According to the invention, these canonical forms also directly imply a second tier of protocols that convert a data stream compliant to one canonical protocol to any of the other canonical protocols. A system according to the invention allows the development of multiple dataflow streams by interconnecting components compliant with one or more of the canonical forms either directly, for components compliant to the same intercommunication protocol, or through the canonical conversions, for components whose intercommunication protocols differ.
Further, the invention provides a mapping between a modeled system and various hardware implementations of the modeled system. This mapping includes low-level hardware for implementing the canonical intercommunication protocols and the canonical conversions between protocols. Target hardware platforms include but are not limited to microprocessor-based systems, programmable logic devices, field programmable gate arrays and application specific integrated circuits.
In another aspect of the invention, consistent with a dataflow approach, a design can be modeled with components having non-static port maps, so that components can derive their parameters, such as bit width, based on the their interconnections with other components. Glue logic, such as that required for the convergence of ready signals can be automatically implied. Moreover, a design targeted to a specific hardware platform can be re-targeted to a different hardware platform by changing the binding of data sources and sinks, making designs re-useable among a plurality of platforms.